1. Field of the Invention
The present invention relates generally to a multichip semiconductor device that is configured so that a semiconductor chip having a function as a CPU or the like and a semiconductor chip as a rewritable memory are connected with each other inside a package.
2. Related Background Art
FIG. 14 is a view schematically illustrating an example of a structure of a conventional multichip semiconductor device. In FIG. 14, the semiconductor device has a chip-on-chip (COC) structure. It should be noted that FIG. 14 illustrates the chips in a side-by-side orientation for convenience in illustration. In the semiconductor device, a first semiconductor chip 1 having a function as a CPU or the like and a second semiconductor chip 2 as a rewritable memory are interconnected via internal connection pads PD1 and PD2 that are provided on the first and second semiconductor chips 1 and 2, respectively, and external connection pads PD 11 of the first semiconductor chip 1 are connected with external connection terminals PD via bonding wires. These chips are sealed in an integrated circuit package 3.
The second semiconductor chip 2 is equipped with a fuse 11 for storing a redundancy restoration solution for restoring defective bits having occurred therein, so as to replace defective bits with cells for redundancy restoration. Semiconductor chips for the two semiconductor chips 1 and 2 are tested independently, and only those that have passed the tests, respectively, are employed to be interconnected. As to the second semiconductor chip 2 as a rewritable memory in particular, semiconductor chips are subjected to a probe test on wafers before the redundancy restoration (hereinafter referred to as P1 test), and then, the fuses 11 of those determined as needing the redundancy restoration are blown. Thereafter, they are subjected to a probe test after the redundancy restoration (hereinafter referred to as P2 test), and the chips that have passed the foregoing test are employed to be interconnected.
In the foregoing COC structure in which pads are provided on surfaces of two semiconductor chips and the two semiconductors are interconnected and connected via the pads, as the number of input/output signals transmitted between the two chips increases, areas of the pads provided on the chips increase relative to the areas of the chips. As a result, there is a possibility that the chip area could be determined according to the pad area.
Furthermore, in the case of a memory chip such as a DRAM, its process cost itself is high, and hence, it is necessary to reduce its size so as to reduce the cost. Therefore, it could be thought of to provide the fuse 11, not on the second semiconductor chip 2 as the rewritable memory as usual, but on the first semiconductor chip 1 having a larger area. However, in this case, the second semiconductor chip 2 alone is not capable of achieving a state after the fuse 11 is blown, and therefore, the P2 test unavoidably is carried out with respect to the second semiconductor chip 2 after the interconnection. As a result, in the case where the second semiconductor chip 2 is found to be defective by the test after the interconnection, a problem arises in that the entire assembly of chips interconnected is wasted as defective.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a multichip semiconductor device with an improved yield and a reduced test cost, by producing a post-redundancy-restoration state of a rewritable memory without providing a fuse on the rewritable memory, so that the P2 test is carried out before interconnecting the chips.
To achieve the foregoing object, a semiconductor device according to the present invention is a multichip semiconductor device that includes a first semiconductor chip and a second semiconductor chip as a rewritable memory that are connected with each other inside a package. In the semiconductor device, the first semiconductor chip has a fuse for redundancy restoration for storing a redundancy restoration solution for restoring defective bits in the second semiconductor chip. Further, the second semiconductor chip includes redundancy cells to be replaced for the defective bits, and has a function of producing a post-redundancy-restoration state in which the defective bits are replaced with the redundancy cells, before being connected with the first semiconductor chip.
With the foregoing configuration, it is possible to allow the second semiconductor chip as a rewritable memory without having a fuse to exhibit a state after the fuse is blown, thereby allowing the execution of the P2 test immediately after the P1 test with respect to the second semiconductor chip. This makes it unnecessary to check whether the redundancy restoration is achieved normally in the second semiconductor chip after the first semiconductor chip and the second semiconductor chip are interconnected with each other. This results in the improvement of the yield of the overall interconnected chips, thereby reducing the inspection cost.
In the semiconductor device according to the present invention, the second semiconductor chip preferably includes a first external input terminal (redundancy restoration solution input pad: PD2D), and a restoration state determining circuit for storing a redundancy restoration solution for restoring the defective bits supplied thereto via the first external input terminal.
In the foregoing configuration, once a redundancy restoration solution is supplied from outside and the restoration state determining circuit stores the redundancy restoration solution, it is possible to produce a post-redundancy-restoration state without continuously supplying the redundancy restoration solution.
Furthermore, in the semiconductor device according to the present invention, the second semiconductor chip preferably includes a second external input terminal (command signal input pad: PD2B), and a control circuit (command decoder circuit) that controls input to the restoration state determining circuit via the first external input terminal according to a signal (command signal) supplied via the second external input terminal.
This configuration allows for the reduction of the number of input terminals necessary for controlling the input of the redundancy restoration solution, as well as allows the post-redundancy-restoration state to be produced after the redundancy restoration state is confirmed completely.
Furthermore, the second semiconductor chip preferably includes a third external input terminal (redundancy restoration execution pad: PD2E) and a memory cell selecting circuit, and the restoration state determining circuit of the second semiconductor chip preferably includes an output circuit that sends the stored redundancy restoration solution to the memory cell selecting circuit according to an input signal (signal RST) supplied via the third external input terminal.
This configuration allows the second semiconductor chip to produce a pre-redundancy-restoration state and the post-redundancy-restoration state by control according to the input signal supplied via the third external input terminal, thereby making it possible to readily find out defects in circuit operations caused by the redundancy restoration.
Furthermore, the restoration state determining circuit of the second semiconductor chip preferably includes a first shift register, and stores serial data supplied via the first external input terminal (redundancy restoration solution input pad: PD2D) in synchronization with an output signal of the control circuit (command decoder circuit).
The foregoing configuration allows the number of input terminals for supplying the redundancy restoration solution to be reduced significantly.
Furthermore, the restoration state determining circuit of the second semiconductor chip preferably includes a plurality of register circuits, and varies a value held by the plurality of register circuits according to an output signal of the control circuit (command decoder circuit), in response to an input signal supplied via the second external input terminal (command signal input pad: PD2B).
This configuration makes it possible to readily test spare cells provided for the redundancy restoration, and in the test, makes it possible to produce a state completely identical to the actual restoration state.
In the semiconductor device according to the present invention, the second semiconductor chip includes: an internal voltage generating circuit including a detection level varying circuit for varying an internal generated voltage; a fourth external input terminal (detection level varying signal input pad: PD2F); and a detection level determining circuit that determines whether the detection level varying circuit is activated, in synchronization with an output signal of the control circuit (command decoder circuit), according to an input signal supplied via the fourth external input terminal.
This configuration makes it possible to vary the detection level of the internal voltage generating circuit, thereby changing an operation of the second semiconductor chip, without changing a physical state, such as blowing a fuse, changing a wiring layer by changing a mask, etc.
In this case, the detection level determining circuit preferably includes second register circuits corresponding to respective generated voltages that can be generated when the internal voltage generating circuit utilizes the detection level varying circuit, and a route changing circuit that changes routes of input signals and output signals to/from the second register circuits according to an input signal supplied via the fourth external input terminal (detection level varying signal input pad: PD2F).
This configuration makes it possible to vary the detection level according to an input signal corresponding to a shift from an original detection level, thereby enabling a test and a variation in the state following the state before the variation.
In the semiconductor device according to the present invention, the second semiconductor chip preferably includes: an internal timing signal generating circuit including a timing changing circuit for adjusting timings; a fifth external input terminal (timing changing signal input pad: PD2G); and an internal timing determining circuit that determines whether the timing changing circuit is activated, in synchronization with an output signal of the control circuit (command decoder circuit), according to an input signal supplied via the fifth external input terminal.
The foregoing configuration makes it possible to readily adjust the internal timing signal as to each of wafers or chips.
In the semiconductor device according to the present invention, the second semiconductor chip includes: an internal voltage generating circuit including a detection level varying circuit for varying an internal generated voltage; a fourth external input terminal (detection level varying signal input pad: PD2F); a detection level determining circuit that determines whether the detection level varying circuit is activated, in synchronization with an output signal of the control circuit (command decoder circuit), according to an input signal supplied via the fourth external input terminal; an internal timing signal generating circuit including a timing changing circuit for adjusting timings; a fifth external input terminal (timing changing signal input pad: (PD2G); an internal timing determining circuit that determines whether the timing changing circuit is activated, in synchronization with an output signal of the control circuit, according to an input signal supplied via the fifth external input terminal; and a first selector circuit. The first selector circuit preferably has a function of selectively supplying a signal supplied via an external address input terminal to the restoration state determining circuit, the detection level determining circuit, and the internal timing determining circuit, according to an output signal of the control circuit.
The foregoing configuration allows for the input of the redundancy restoration solution, the variation of the detection level of the internal generated voltage, or the signal input for changing the internal timing, without increasing the number of external input terminals.